1. Field of the Invention
The present invention relates to a method for forming a DRAM cell and, more particularly, to a method for forming a DRAM cell with a stacked capacitor.
2. Description of the Related Art
A dynamic random-access-memory (DRAM) cell is a semiconductor memory device that only temporarily stores information and, therefore, must be periodically refreshed to insure that the information stored in the cell is properly retained.
FIG. 1 shows a cross-sectional view that illustrates a conventional DRAM cell 10. As shown in FIG. 1, DRAM cell 10 includes an access transistor 12 which has spaced-apart n+ source and drain regions 14 and 16 which are formed in a p-type semiconductor substrate 18.
In addition, transistor 12 also includes a channel region 20 which is defined in substrate 18 between the source and drain regions 14 and 16, a layer of gate oxide 22 formed above channel region 20, and a gate 24 which is formed over oxide layer 20.
As further shown in FIG. 1, cell 10 also includes a capacitor 30 which has a lower plate 32 that is formed to contact drain region 16, and an upper plate 34 which is insulatively formed over lower plate 32. In addition, transistor 12 is insulated from surrounding structures, including capacitor 30, by a layer of insulation material 36.
In operation, cell 10 is programmed by applying a first programming voltage to gate 24, and a second programming voltage to source region 14. In addition, a capacitor voltage is continuously applied to upper plate 34.
In response to these biasing conditions, channel region 20 inverts which allows majority carriers (electrons) from drain region 16 to flow to source region 14. As a result of the loss of electrons from drain region 16, the potential on drain region 16 is increased.
Cell 10 is erased by reversing the process and applying an erase voltage to gate 24, and ground to source region 14. In this case, channel region 20 is again inverted, but the higher potential on drain region 16 causes the electrons to flow from source region 14 to drain region 16.
Cell 10 is read by applying a read voltage to gate 24, and connecting source region 14 to a sense amplifier (not shown). In response to these biasing conditions, the potential on drain region 16 appears on source region 14, less the threshold voltage of access transistor 12, which is then detected by the sense amplifier.
One problem with conventional DRAM cells is that as the area consumed by a cell is reduced in size, the area available to the capacitor is also reduced in size which, in turn, limits the ability of the cell to maintain a programmed state. One solution to this problem has been to vertically increase the size of the capacitor by using a stacked capacitor.
FIG. 2 shows a cross-sectional view that illustrates a conventional stacked-capacitor DRAM cell 50. As shown in FIG. 2, DRAM cell 50 is similar to cell 10 and, as a result, utilizes the same reference numerals to identify the structures which are common to both cells.
DRAM cell 50 principally differs from cell 10 in that cell 50 utilizes a stacked capacitor 52 which has a lower plate 54 that is formed to have a series of fins or wings 56, and an upper plate 60 which is insulatively formed over lower plate 54. In addition, cell 50 also utilizes a layer of nitride 62 which is formed over the portion of insulation layer 36 that supports capacitor 52.
By utilizing stacked capacitor 52, the size of the capacitor can be significantly increased without consuming any additional cell area. As a result, the dimensions of cell 50 can be reduced without reducing the capacitance provided by the cell.
FIGS. 3A-3H shows cross-sectional views that illustrate the fabrication of DRAM cell 50. As shown in FIG. 3A, conventional steps are used to fabricate transistor 12 and the overlying layer of insulation material 36.
Once the conventional steps have been completed, nitride layer 62 is deposited over insulation layer 36. After this, a layer of sacrificial oxide 64 is formed over nitride layer 62, followed by the deposition of an overlying layer of polysilicon (poly) 66. Next, a second layer of sacrificial oxide 70 is formed over poly layer 66, followed by the formation and patterning of a contact mask 72 over oxide layer 70.
After this, as shown in FIG. 3B, oxide layer 70, poly layer 66, oxide layer 64, nitride layer 62, and insulation layer 36 are anisotropically etched to form a contact opening 74 that exposes a contact area 76 on the surface of drain region 16. Once contact opening 74 has been formed, mask 72 is removed.
Next, as shown in FIG. 3C, a layer of poly 80 is deposited over oxide layer 70, the sidewalls of contact opening 74, and contact area 76. Following this, a lower plate mask 82 is formed and patterned over poly layer 80.
Once mask 82 has been formed, as shown in FIG. 3D, poly layer 80, oxide layer 70, poly layer 66, and a portion of oxide layer 64 are anisotropically etched to define the size of lower plate 54. After this, mask 82 is removed.
Once mask 82 has been removed, as shown in FIG. 3E, the resulting structure is isotropically etched to remove the remainder of oxide layer 64 and oxide layer 70. During this etching step, nitride layer 62 is used as an etch stop to protect the underlying layer of insulation material 36. (Mask 82 may alternately be removed following the isotropic etch step).
Turning now to FIG. 3F, after the isotropic etch step has been completed, a thin layer of dielectric 84 is formed on the exposed surfaces of poly layers 66 and 80. Following this, a layer of poly 86 is then deposited over nitride layer 62 and dielectric layer 84. Next, an upper electrode mask 90 is formed and patterned over poly layer 86.
Once mask 90 has been formed, as shown in FIG. 3G, the unmasked layer of poly 86 is etched to form upper plate 60. Conventional back end processing steps are then followed to complete the fabrication of the cell.
As noted above, conventional steps are utilized to form access transistor 12. In addition to forming access transistor 12, the same process steps are also utilized to fabricate the CMOS transistors that form the peripheral circuitry, e.g., the row and column decoders, that support an array of DRAM cells.
Conventionally, the gates of the peripheral CMOS transistors are all doped to have the same type of conductivity. More recently, however, the peripheral CMOS transistors are formed to have dual-work function gates where the gates of the NMOS transistors are implanted with an n-type material, such as phosphorous, and the gates of the PMOS transistors are implanted with a p-type material, such as boron.
One problem with the above-described fabrication process is that, during the formation of nitride layer 62, hydrogen is trapped below nitride layer 62. The hydrogen migrates down during the subsequent fabrication steps and enhances the diffusion of boron from the gates to the underlying layer of gate oxide which, in turn, undesirably alters the threshold voltages of the PMOS transistors.
One technique for reducing this hydrogen-enhanced boron diffusion is to remove the exposed portion of nitride layer 62 during the etching step that is used to form the upper plate 60 of capacitor 52 as shown in FIG. 3H.
Although removing the exposed portion of nitride layer 62 reduces the problem, there is a need for other techniques that further reduce or eliminate the problem of hydrogen-enhanced boron diffusion.